XR16V2752_07 Datasheet, PDF (3/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

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PIN DESCRIPTIONS
XR16V2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Pin Description
NAME
32-QFN
PIN #
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
7
15
A1
6
14
A0
3
10
D7
2
9
D6
1
8
D5
32
7
D4
31
6
D3
30
5
D2
29
4
D1
28
3
D0
27
2
IOR#
14
24
IOW#
11
20
CS#
10
18
CHSEL
8
16
INTA
21
34
INTB
9
17
TXRDYA#
-
1
I Address data lines [2:0]. These 3 address lines select one of the internal
registers in UART channel A/B during a data bus transaction.
I/O Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge instigates an inter-
nal read cycle and retrieves the data byte from an internal register pointed
to by the address lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
I Input/Output Write Strobe (active low). The falling edge instigates an inter-
nal write cycle and the rising edge transfers the data byte on the data bus
to an internal register pointed by the address lines.
I UART chip select (active low). This function selects channel A or B in
accordance with the logical state of the CHSEL pin. This allows data to be
transferred between the user CPU and the 2752.
I Channel Select - UART channel A or B is selected by the logical state of
this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the
UART channel B while a logic 1 selects UART channel A. Normally,
CHSEL could just be an address line from the user CPU such as A4. Bit-0
of the Alternate Function Register (AFR) can temporarily override CHSEL
function, allowing the user to write to both channel register simultaneously
with one write cycle when CS# is low. It is especially useful during the ini-
tialization routine.
O UART channel A Interrupt output (active high). A logic high indicates chan-
nel A is requesting for service. For more details, see Figures 17- 22.
O UART channel B Interrupt output (active high). A logic high indicates chan-
nel B is requesting for service. For more details, see Figures 17- 22.
O _{UART channel A Transmitter Ready (active low). The output provides the}
TX FIFO/THR status for transmit channel A. See Table 2.
TXRDYB#
-
32
O
MODEM OR SERIAL I/O INTERFACE
TXA
23
38
O
UART channel B Transmitter Ready (active low). The output provides the
TX FIFO/THR status for transmit channel B. See Table 2.
UART channel A Transmit Data or infrared encoder data. Standard trans-
mit and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit
and receive interface is enabled when MCR[6] = 1. In the Infrared mode,
the inactive state (no data) for the Infrared encoder/decoder interface is
LOW. If it is not used, leave it unconnected.
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