XR16V2752_07 Datasheet, PDF (46/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16V2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.1
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WRI
TX FIFO drops
below trigger level
T_WT
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
TX FIFO
Empty
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Start
Bit
Stop
Bit
TX
(Unloading)
S D0:D7 T S D0:D7 T
IER[1]
enabled
ISR Read
D0:D7 S D0:D7 T
S D0:D7 T S D0:D7 T
T_SRT
T_SI
Last Data Byte
Transmitted
S D0:D7 T
ISR Read
INT*
TXRDY#
TX FIFO fills up
to trigger level
T_WRI
TX FIFO
Full
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T_WT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
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