XR16V2752_07 Datasheet, PDF (28/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16V2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.1
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER FCTR FCTR FCR
TABLE BIT-5 BIT-4 BIT-7
Table-A 0
0
0
0
1
1
Table-B 0
1
0
0
1
1
Table-C 1
0
0
0
1
1
Table-D 1
1
X
FCR
BIT-6
0
1
0
1
0
1
0
1
0
1
0
1
X
FCR
BIT-5
0
0
0
1
1
0
0
1
1
X
FCR
RECEIVE
BIT-4 TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
0
1 (default) 16C550, 16C2550,
1 (default)
4
16C2552, 16C554,
16C580
8
14
0
1
0
1
8
16
24
28
16
16C650A
8
24
30
0
1
0
1
8
16
56
60
8
16C654
16
32
56
X Programmable Programmable 16L2752, 16C2850,
via TRG
register.
via TRG
register.
16C2852, 16C850,
16C854, 16C864
FCTR[7] = 0. FCTR[7] = 1.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
28