XR16L651 Datasheet, PDF (51/56 Pages) Exar Corporation – 2.25V TO 5.5V UART WITH 32-BYTE FIFO

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REV. 1.3.0
XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
FIGURE 29. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
RX
INT
RXRDY#
Start
Bit
Stop
Bit
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
T_SSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
T_SSR
Timeout
FIFO
Empties
IOR#
(Reading data out
of RX FIFO)
T_RRI
T_RR
IOR# is shown here as an example. IOR would have the same timing as IOR#, but active high.
RXFIFODMA
FIGURE 30. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
TX FIFO
Empty
TX
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WRI
TX FIFO drops
below trigger level
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
IOW# is shown here as an example. IOW would have the same timing as IOW#, but active high.
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
TX FIFO
Empty
TXDMA#
51