XR16L651 Datasheet, PDF (50/56 Pages) Exar Corporation – 2.25V TO 5.5V UART WITH 32-BYTE FIFO

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
FIGURE 27. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]
TX
(Unloading)
IER[1]
enabled
Start
Bit
D0:D7
Stop
Bit
ISR is read
D0:D7
ISR is read
INT*
T_WRI
TXRDY#
T_WRI
T_SRT
T_SRT
T_WRI
áç
REV. 1.3.0
D0:D7
ISR is read
T_SRT
T_WT
T_WT
T_WT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
IOW# is shown here as an example. IOW would have the same timing as IOW#, but active high.
TXNonFIFO
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
Start
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
Stop
Bit
INT
T_SSR
RXRDY#
First Byte is
Received in
RX FIFO
T_SSI
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
T_RRI
T_RR
IOR#
(Reading data out
of RX FIFO)
IOR# is shown here as an example. IOR would have the same timing as IOR#, but active high.
RXINTDMA#
50