XR16L651 Datasheet, PDF (32/56 Pages) Exar Corporation – 2.25V TO 5.5V UART WITH 32-BYTE FIFO

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 1.3.0
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 is the default unless the IR mode is forced by the ENIR pin. This bit can overwrite the ENIR state after
a power up or reset.
• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The infrared TX output is at logic 0 during idle condition. The infrared receive data input polarity
is also logic 0, however, it may be inverted when using an infrared module that provides inverted signal
output. Use register XFR bit-1 to invert the receive input signal level going to the infrared decoder. Also see
XFR bit-0 for half-duplex operation where the receiver can be disabled while transmitting.
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or RX FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or RX FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error. If IER bit-2 is enabled, an interrupt is
generated immediately.
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If IER bit-2 is enabled, an interrupt
is generated when the character is available in the RHR (XFR[3] = 0) or when the character is received
(XFR[3] = 1).
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If IER bit-2 is enabled, an interrupt is generated when the
character is available in the RHR (XFR[3] = 0) or when the character is received (XFR[3] = 1).
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication is cleared when LSR is
read, but the RX input may still be a logic 0. If IER bit-2 is enabled, an interrupt is generated when the
character is available in the RHR (XFR[3] = 0) or when the character is received (XFR[3] = 1).
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