XR16L651 Datasheet, PDF (4/56 Pages) Exar Corporation – 2.25V TO 5.5V UART WITH 32-BYTE FIFO

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 1.3.0
NAME
PIN #
TYPE
DESCRIPTION
CS0
9
I Chip Select 0 input (active high)
This input selects the XR16L651 device. If CS1 or CS2# is used as the chip
select then this pin must be connected to VCC. The 651 is selected when all
three chip selects are active. See Figure 3 through Figure 5.
CS1
10
I Chip Select 1 input (active high)
This input selects the XR16L651 device. If CS0 or CS2# is used as the chip
select then this pin must be connected to VCC. The 651 is selected when all
three chip selects are active. See Figure 3 through Figure 5.
CS2#
11
I Chip Select 2 input (active low)
This input selects the XR16L651 device. If CS0 or CS1 is used as the chip
select then this pin must be connected to GND. The 651 is selected when all
three chip selects are active. See Figure 3 through Figure 5.
INT
(INT#)
30
O Interrupt Output
This output becomes active whenever the transmitter, receiver, line and/or
modem status register has an active condition. See interrupt section for more
details. When IM# pin is at logic 0 (Intel bus mode), this interrupt output may
be set to normal active high or active high open source to provide wire-OR
capability by connecting a 1k to 10k ohms resistor between this pin and
ground. When IM# pin is at logic 1 (Motorola bus mode), this interrupt output
becomes an open drain, active low output. It requires an external pull-up
resistor of 1K-10K ohms to operate properly. The output may be wire-OR’ed
with other devices in the system to form a single interrupt request to the host
processor and have the software driver poll all devices to determine the inter-
rupting condition(s).
AS#
24
I Address Strobe input (active low)
In the Intel bus mode, the leading-edge transition of AS# latches the chip
selects (CS0, CS1, CS2#) and the address lines A0, A1 and A2. This input is
used when the address lines are not stable for the duration of a read or write
operation. In devices with top mark date code of "C2 YYWW" and newer, the
address bus is latched even if this input is not used. These devices feature a
’0 ns’ address hold time. See “AC Electrical Characteristics” .
If not required, this input can be permanently tied to GND. This input is not
used in the Motorola mode.
TXRDY#
23
O UART Transmitter Ready (active low)
The output provides the TX FIFO/THR status. See Table 2. If it is not used,
leave it unconnected.
RXRDY#
29
O UART Receiver Ready (active low)
This output provides the RX FIFO/RHR status for receive channel A. See
Table 2. If it is not used, leave it unconnected.
PC Mode Interface Signals. Connect PCMODE# pin to GND and IM# pin to GND to select PC Mode.
A3
20
I PC mode additional Address Lines
A4
6
In the PC mode, these are the additional address lines from the host address
A5
9
A6
10
A7
11
bus. They are inputs to the on-board chip select decode function for COM 1-4
and LPT ports. See Table 1 for details. The pins A4 and A9 have internal
100kΩ pull-up resistors.
A8
17
A9
38
4