XR16L651 Datasheet, PDF (33/56 Pages) Exar Corporation – 2.25V TO 5.5V UART WITH 32-BYTE FIFO

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REV. 1.3.0
XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: Transmit Shift Register Empty Flag
This bit is the Transmit Shift Register Empty indicator. This bit is set to a logic 1 whenever the transmitter goes
idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is
set to one whenever the transmit FIFO and transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.9 Extra Feature Register (XFR) - Write Only
This register provides additional features and controls to the XR16L651 UART.
XFR [0]: Half-duplex Infrared Mode Enable
When infrared mode is enabled, MCR bit-6=1, this bit selects the infrared mode to operate in normal full-duplex
or half-duplex mode. This half-duplex mode feature is very desirable when the UART does not want to “see” its
own data that may be reflected.
• Logic 0 = Disable. The receiver is active during data transmission.
• Logic 1 = Enable half-duplex operation. The infrared receiver is disabled during data transmission.
XFR [1]: Invert Received Infrared Input Signal
This bit controls the input polarity of the infrared data.
• Logic 0 = Infrared data input idles at logic 0 (default).
• Logic 1 = Infrared data idles at logic 1, pulses low.
XFR [2]: Auto RS485 Enable
This bit enables the auto RS485 direction control feature for half-duplex operation with RS-485 transceiver.
The feature should only be enabled when normal RTS# output and auto RTS flow control are not used.
• Logic 0 = Disable the auto RS485 direction control function. This allows normal RTS# output or auto RTS
flow control operation.
• Logic 1 = Enable the auto RS485 direction function. The RTS# output will automatically change its logic state
to control the RS-485 transceiver from sending and receiving. See “Auto RS485 Half-duplex Control” on
page 19.
XFR [3]: LSR Bad Data Interrupt Operation
When the LSR interrupt is enabled, IER bit-2=1, this bit selects when the interrupt pin (INT) will report received
character error: parity, framing or break. Use this feature only if application needs immediate knowledge when
a bad character is received.
• Logic 0 = Received data error interrupt (LSR interrupt) will be generated when the bad character is available
for reading from the FIFO. This is compatible to industry standard 16C550 operation.
• Logic 1 = Received data error interrupt (LSR interrupt) is generated immediately upon receipt of the bad
character. It will be reset when LSR is read. If user does not read the bad character out, another bad
character interrupt is generated when it’s available for reading from the FIFO.
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