XRT73L00A Datasheet, PDF (47/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
5.0 THE MICROPROCESSOR SERIAL INTER-
FACE
The on-chip Command Registers of the XRT73L00A
DS3/E3/STS-1 Line Interface Unit IC are accessed to
configure the XRT73L00A into a variety of modes.
This section describes the Command Registers and
how to use the Microprocessor Serial Interface.
5.1 DESCRIPTION OF THE COMMAND REGISTERS
A listing of these Command Registers, their Address-
es and their Bit-Formats are listed in Table 5.
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73L00A COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS COMMAND REGISTER
TYPE
D4
D3
D2
D1
D0
0x00
CR0
RO
RLOL
RLOS
ALOS
DLOS
DMO
0x01
CR1
R/W
TXOFF
TAOS
TXCLKINV TXLEV
TXBIN
0x02
CR2
R/W
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
0x03
CR3
R/W
RNRZ
LOSMUT RCLK2/LCV RCLK2INV RCLK1INV
0x04
CR4
R/W
Reserved STS-1/DS3
E3
LLB
RLB
0x05
CR5
R/W
Reserved Reserved Reserved Reserved Reserved
0x06
CR6
R/W
Reserved Reserved Reserved Reserved Reserved
0x07
CR7
R/W
Reserved Reserved Reserved Reserved Reserved
0x08
CR8
R/W
Reserved Reserved Reserved Reserved Reserved
0x09
CR9
R/W
Reserved Reserved Reserved Reserved Reserved
0x10
CR10
R/W
Reserved Reserved Reserved Reserved Reserved
0x11
CR11
R/W
Reserved Reserved Reserved Reserved Reserved
0x12
CR12
R/W
Reserved Reserved Reserved Reserved Reserved
0x13
CR13
R/W
Reserved Reserved Reserved Reserved Reserved
0x14
CR14
R/W
Reserved Reserved Reserved Reserved Reserved
0x15
CR15
R/W
Reserved Reserved Reserved Reserved Reserved
Address:
The register addresses are in Hexadecimal format.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) registers.
NOTES:
1. The default value for each of the bit-fields in these
registers is “0”.
2. If the REGRESET input pin is asserted, then the
contents of the command registers is reset to all
"0's" resulting in the XRT73L00A operating in the
mode corresponding to the default values of the
Command Registers.
DESCRIPTION OF BIT-FIELDS FOR EACH COM-
MAND REGISTER
5.1.1 Command Register - CR0
Bit D4 - RLOL (Receive Loss of Lock Status)
This Read-Only bit-field reflects the lock status of the
Clock Recovery Phase-Locked-Loop in the
XRT73L00A.
This bit-field is set to “0” if the Clock Recovery PLL is
in lock with the incoming line signal. This bit-field is
set to “1” if the Clock Recovery PLL is out of lock with
the incoming line signal.
Bit D3 - RLOS (Receive Loss of Signal Status)
This Read-Only bit-field indicates whether or not the
Receiver in the XRT73L00A is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field is set to “0” if the XRT73L00A is not cur-
rently declaring the LOS Condition. This bit-field is
set to “1” if the XRT73L00A is declaring an LOS Con-
dition.
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