XRT73L00A Datasheet, PDF (46/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
áç
FIGURE 33. TWO LIU’S, EACH MONITORING THE TRANSMIT OUTPUT SIGNAL OF THE OTHER LIU IC
DMO_Channel_2
U1
DMO
TXOFF
U2
DMO_Channel_1
TXOFF
DMO
TTIP
TRING
MTIP
MRING
R3
270 Ω
R4
270 Ω
MRING
MTIP
TRING
R5
270 Ω
R6
270 Ω
TTIP
R1
31.6Ω
R2
31.6Ω
T1
BNC
PE-68629
R7
31.6Ω
R8
31.6Ω
T2
BNC
PE-68629
Presented in Figure 33, if LIU # 1 (U1) fails, then LIU
# 2 (U2) drives its DMO output pin “High”. Likewise, if
LIU # 2 (U2) fails, then LIU # 1 (U1) drives its DMO
output pin “High”.
The scheme presented in Figure 33 is a better design
approach. It overcomes situations in which a LIU
monitoring its own signal (Figure 32) may experience
a failure mode such that it cannot drive a bipolar sig-
nal onto the line. That same failure mode may pre-
vent the LIU from driving the DMO output pin “High”.
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT73L00A can transmit an all “1’s” pattern onto
the line by toggling a single input pin or by setting a
single bit-field in one of the Command Registers to
“1”.
NOTE: When this feature is activated, the Transmit Section
of the XRT73L00A overwrites the Terminal Equipment data
with this all “1’s” pattern.
This feature can be activated by either of the following
methods.
When the XRT73L00A is operating in the Hard-
ware Mode:
Configure the device to transmit an all “1’s” pattern by
toggling the TAOS input pin (pin 2) “High”. Terminate
the all “1’s” pattern by toggling the TAOS input pin
“Low”.
When the XRT73L00A is operating in the HOST
Mode:
If the XRT73L00A is operating in the HOST Mode,
the TAOS input pin is disabled. Consequently, the
XRT73L00A can be configured to transmit an all “1’s”
pattern by writing to Command Register CR1 and set-
ting the TAOS bit-field (bit D3) to “1”.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
0
1
X
X
X
The all “1’s” pattern can be terminated by writing to
Command Register CR1 and setting the TAOS bit-
field (D3) to “0".
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