XRT73L00A Datasheet, PDF (42/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
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Figure 29 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT73L00A can be configured to operate in the
Analog Local Loop-Back Mode by employing either
one of the following two steps:
FIGURE 29. THE ANALOG LOCAL LOOP-BACK IN THE XRT73L00A
RLOL EXCLK
RTIP
RRING
REQDIS
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
TTIP
TRING
TXLEV
TXOFF
DMO
AGC/
Equalizer
Slicer
Clock
Recovery
Peak
Detector
LOS Detector
Data
Recovery
Serial
Processor
Interface
Analog Local
Loop-Back Path
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
MTIP
MRING
If the XRT73L00A is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the LLB bit-field and a “0” into the RLB bit-
field in Command Register 4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X STS-1/DS3
E3
LLB
RLB
X
X
X
1
0
If the XRT73L00A is operating in the Hardware
Mode:
The LLB input pin (pin 14) must be set to “High” and
the RLB input pin (pin 15) must be set to “Low”.
NOTES:
1. The Analog Local Loop-Back Mode does not work
if the transmitter is turned off via the TXOFF fea-
ture.
2. The XRT73L00A automatically Declares an LOS
Condition anytime it has been configured to oper-
ate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the Muting
-upon -LOS must be disabled prior to configuring
the device to operate in either of these local Loop-
Back modes.
4.2 THE DIGITAL LOCAL LOOP-BACK MODE
When the XRT73L00A is configured to operate in the
Digital Local Loop-Back Mode, it ignores any signals
that are input to the RTIP and RRING input pins. The
Transmitting Terminal Equipment transmits clock and
data into the XRT73L00A via the TPDATA, TNDATA
and TCLK input pins. This data is processed through
the Transmit Clock Duty Cycle Adjust PLL and the
HDB3/B3ZS Encoder block and then looped back to
the HDB3/B3ZS Decoder block.
Figure 30 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
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