XRT73L00A Datasheet, PDF (34/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
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NOTES:
1. If the Receive Equalizer block is turned ON in a
given Receive Section that is receiving a line signal
over short cable length, there is the risk of over-
equalizing the received line signal which could
degrade performance by increasing the amount of
jitter that exists in the recovered data and clock sig-
nals or by creating bit-errors.
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the Trans-
mitting Terminal to the Receiving Terminal. How-
ever, Receive Equalizer was not designed to
counter flat loss where all of the Fourier frequency
components in the line signal are subject to the
same amount of attenuation. Flat loss is handled
by the AGC block.
The Receive Equalizer block can be disabled setting
the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bit-
field in Command Register CR2 when operating the
XRT73L00A in the HOST Mode.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
X
X
X
1
3.3 PEAK DETECTOR AND SLICER
After the incoming line signal has passed through the
Receive Equalizer, it is routed to the Slicer block. The
purpose of the Slicer is to quantify a given bit-period
or symbol within the incoming line signal as either a
“1” or a “0”.
3.4 CLOCK RECOVERY PLL
The output of the Slicer, which is now Dual-Rail digital
pulses, is routed to the Clock Recovery PLL. The
purpose of the Clock Recovery PLL is to track the in-
coming Dual-Rail data stream and to derive and gen-
erate a recovered clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the EXCLK input pin.
The Clock Recovery PLL operates in one of two
modes:
• The Training Mode.
• The Data/Clock Recovery Mode
1. The Training Mode
If the XRT73L00A is not receiving a line signal via the
RTIP and RRING input pins or if the frequency differ-
ence between the line signal and that applied via the
EXCLK input pin exceeds 0.5%, then the XRT73L00A
LIU IC is operating in the Training Mode. When the
LIU is operating in the Training Mode it does the fol-
lowing:
A. declares a Loss of Lock indication by toggling the
RLOL output pin “High” and
B. outputs a clock signal via the RCLK1 and RCLK2
output pins which is derived from the signal ap-
plied to the EXCLK input pin.
2. The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXCLK input pin is less than
0.5%, the XRT73L00A LIU IC is operating in the Da-
ta/Clock Recovery Mode. In this mode, the Clock Re-
covery PLL is locked onto the line signal via the RTIP
and RRING input pins.
3.5 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data in the
Near-End Receiving Terminal. Once the data has
made it across the E3, DS3 or STS-1 Transport Medi-
um and has been recovered by the Clock Recovery
PLL, it is now necessary to restore the original con-
tent of the data. The purpose of the HDB3/B3ZS De-
coding block is to restore the data transmitted over
the E3, DS3 or STS-1 line to its original content prior
to Zero Suppression encoding.
3.5.1 B3ZS Decoding DS3/STS-1 Applications
If the XRT73L00A is configured to operate in the DS3
or STS-1 Modes, then the HDB3/B3ZS Decoding
Block performs B3ZS Decoding. When the Decoder
is operating in this mode it parses through the incom-
ing Dual-Rail data and checks for the occurrence of
either a “00V” or a “B0V” pattern. If the B3ZS Decod-
er detects this particular pattern it substitutes these
bits with a “000” pattern.
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the”B3ZS Line Code” format,
or if the B3ZS Decoder detects a string of 3 (or more) con-
secutive “0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by puls-
ing the LCV output pin “High”.
Figure 20 illustrates the B3ZS Decoder at work with
two separate Zero Suppression patterns in the in-
coming Dual-Rail Data Stream.
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