XRT73L00A Datasheet, PDF (31/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
3.0 THE RECEIVE SECTION
Figure 1 indicates that the XRT73L00A Receive Sec-
tion consists of the following blocks:
• AGC/Equalizer
• Peak Detector
• Slicer
• Clock Recovery PLL
• Data Recovery
• HDB3/B3ZS Decoder
The purpose of the XRT73L00A Receive Section is to
take an incoming attenuated/distorted bipolar signal
from the line and encode it back into the TTL/CMOS
format where it can be received and processed by
digital circuitry in the Terminal Equipment.
3.1 INTERFACING THE RECEIVE SECTION OF THE
XRT73L00A TO THE LINE
By design, the Receive Section of the XRT73L00A
can be transformer-coupled or capacitive-coupled to
the line. The specification documents for E3, DS3
and STS-1 all specify 75Ohm termination loads when
transmitting over coaxial cable. It is recommended to
interface the Receive Section of the XRT73L00A to
the line as shown in Figure 17 or Figure 18.
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L00A TO THE
LINE (TRANSFORMER-COUPLING)
RxPOS
RxNEG
RxLineClk
RxLOS
RxLOL
RPOS
RNEG
RCLK1
RTIP
R1
37.4Ω
RLOS
RLOL
R2
37.4Ω
RRING
C1
0.01uf
BNC
T2
1:1
FIGURE 18. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L00A TO THE
LINE (CAPACITIVE-COUPLING)
RTIP
C1
0.01uF
R1
75Ω
Receive Line Signal
RRING
C2
0.01uF
3.2 THE RECEIVE EQUALIZER BLOCK
After the XRT73L00A has received the incoming line
signal via the RTIP and RRING input pins, the first
block that this signal passes through is the AGC (Au-
tomatic Gain Control) circuit followed by the Receive
Equalizer.
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