XR16C2852_05 Datasheet, PDF (44/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
xr
REV. 2.1.1
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Start
Bit
D0:D7
Stop
Bit
D0:D7
D0:D7
T_SSR
T_SSR
T_SSR
1 Byte
1 Byte
1 Byte
INT
in RHR
in RHR
in RHR
T_SSR
T_SSR
T_SSR
RXRDY#
Active
Data
Ready
T_RR
Active
Data
Ready
T_RR
Active
Data
Ready
T_RR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
(Unloading)
IER[1]
enabled
Start
Bit
D0:D7
Stop
Bit
ISR is read
D0:D7
ISR is read
D0:D7
ISR is read
INT*
T_WRI
TXRDY#
T_WRI
T_SRT
T_SRT
T_WRI
T_SRT
T_WT
T_WT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
T_WT
TXNonFIFO
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