XR16C2852_05 Datasheet, PDF (37/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls
below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take
effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.21 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 6 on page 17.
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