XR16C2852_05 Datasheet, PDF (11/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
divisor between 1 and (2¹⁶ -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate
clock is used by the transmitter for data bit shifting and receiver for data sampling.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL and DLM
Registers
MCR Bit-7=0
(default)
Baud Rate
Generator
Logic
MCR Bit-7=1
16X
Sampling
Rate Clock to
Transmitter
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
MCR Bit-7=1
MCR Bit-7=0 ^{DIVISOR FOR 16x DIVISOR FOR 16x}
Clock (Decimal) Clock (HEX)
(DEFAULT)
100
400
2304
900
600
2400
384
180
1200
4800
192
C0
2400
9600
96
60
4800
19.2k
48
30
9600
38.4k
24
18
19.2k
76.8k
12
0C
38.4k
153.6k
6
06
57.6k
230.4k
4
04
115.2k
460.8k
2
02
230.4k
921.6k
1
01
DLM
PROGRAM
VALUE (HEX)
09
01
00
00
00
00
00
00
00
00
00
DLL
PROGRAM
VALUE (HEX)
00
80
C0
60
30
18
0C
06
04
02
01
DATA RATE
ERROR (%)
0
0
0
0
0
0
0
0
0
0
0
2.11 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
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