XR16C2852_05 Datasheet, PDF (3/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
15
I Address data lines [2:0]. These 3 address lines select one of the internal registers in
A1
14
UART channel A/B during a data bus transaction.
A0
10
D7
9
I/O Data bus lines [7:0] (bidirectional).
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
IOR#
24
I Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
20
I Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
18
I UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the 2852.
CHSEL
16
I Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is LOW. A LOW on the CHSEL selects the UART channel B while a HIGH
selects UART channel A. Normally, CHSEL could just be an address line from the
user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily
override CHSEL function, allowing the user to write to both channel register simulta-
neously with one write cycle when CS# is LOW. It is especially useful during the ini-
tialization routine.
INTA
34
O UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures 20- 25.
INTB
17
O UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures 20- 25.
TXRDYA#
1
O UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. See Table 2 on page 9. If this output is
not used, leave it unconnected.
TXRDYB#
32
O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. See Table 2 on page 9. If this output is not
used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
38
O _{UART channel A Transmit Data or infrared encoder data. Standard transmit and}
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If this output is not used, leave it
unconnected.
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