XR16C2852_05 Datasheet, PDF (41/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
AC ELECTRICAL CHARACTERISTICS
TA=0^O TO 70^OC (-40^O TO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
CONDITIONS
CLK Clock Pulse Duration
30
20
ns
OSC Oscillator Frequency
8
24 MHz
OSC External Clock Frequency
33
50 MHz
T_AS Address Setup Time
10
5
ns
T_AH Address Hold Time (AS# tied to GND)
10
5
ns
(top mark date code of "DC YYWW" and older)
T_AH Address Hold Time (AS# tied to GND)
0
(top mark date code of "F2 YYWW" and newer)
0
ns
T_CS Chip Select Width
66
50
ns
T_RD IOR# Strobe Width
35
25
ns
T_DY Read Cycle Delay
40
30
ns
T_RDV Data Access Time
50
35
ns
T_DD Data Disable Time
0
35
0
25
ns
T_WR IOW# Strobe Width
40
25
ns
T_DY Write Cycle Delay
40
30
ns
T_DS Data Setup Time
10
5
ns
T_DH Data Hold Time
10
5
ns
T_WDO Delay From IOW# To Output
50
40
ns 100 pF load
T_MOD Delay To Set Interrupt From MODEM Input
40
35
ns 100 pF load
T_RSI Delay To Reset Interrupt From IOR#
40
35
ns 100 pF load
T_SSI Delay From Stop To Set Interrupt
1
1
Bclk
T_RRI Delay From IOR# To Reset Interrupt
45
40
ns 100 pF load
T_SI Delay From Stop To Interrupt
45
40
ns
T_INT Delay From Initial INT Reset To Transmit Start
8
24
8
24 Bclk
T_WRI Delay From IOW# To Reset Interrupt
45
40
ns
T_SSR Delay From Stop To Set RXRDY#
1
1
Bclk
T_RR Delay From IOR# To Reset RXRDY#
45
40
ns
T_WT Delay From IOW# To Set TXRDY#
45
40
ns
41