XRT79L74 Datasheet, PDF (40/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L74
REV. P1.0.0
PIN #
B14
C14
A15
B15
C15
NAME
RxAddr_0
RxAddr_1
RxAddr_2
RxAddr_3
RxAddr_4
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
I
DESCRIPTION
Receive UTOPIA Interface Address Bus input pins/Receive POS-PHY
Interface Address Bus Input pins:
The exact function of these input pins depends upon whether the XRT79L74
device has been configured to operate in the ATM UNI or PPP Modes.
ATM UNI Modes - RxUAddr[4:0] - Receive UTOPIA Address Bus:
These input pins functions as the Receive UTOPIA Address bus inputs. These
input pins are only active when the XRT79L74 device is operating in both the
ATM UNI and Multi-PHY Modes. Whenever the ATM Layer Processor wishes
to poll or read data from a particular UNI (PHY-Layer) device, it will provide the
"UTOPIA Address" of the "target" PHY-Layer device on the Receive UTOPIA
Address Bus. The Receive UTOPIA Address Bus input is sampled on the rising
edge of the RxUClk signal. Each time the Receive UTOPIA Interface block
samples the "Receive UTOPIA Address Bus", the contents of this address bus
are compared with the pre-programmed UTOPIA Address value (which was
loaded into the XRT79L74 device by writing the appropriate data into both the
"Receive UTOPIA Port Address" Register (Address = 0x0513) and the "Receive
UTOPIA Port Number" Register (Address = 0x0517). If these two values
match, and the RxUENB* input pin is asserted, then the RxUClav output pin will
be driven to the appropriate state (based upon the RxFIFO fill level). If these
two address values do not match, then the Receive UTOPIA Interface block will
continue to tri-state the "RxUClav" output pin.
NOTE:
These input pins are only active if the XRT79L74 device has been
designed into a "Multi-PHY" Application. If the user intends to design
the XRT79L74 device into a "Single-PHY" Application, then he/she
should tie these input pins to GND.
PPP Mode - RxPAddr[4:0] - Receive POS-PHY Interface Address Bus Input
Pins:
These input pins comprise the Receive POS-PHY Address Bus input pins.
Whenever the Link Layer Processor wishes to poll or read PPP packet data
from a particular PHY-Layer device, it will provide the address of the "target
PHY-Layer device" on the Receive POS-PHY Address Bus. The contents of the
Receive POS-PHY Address Bus input pins are sampled on the rising edge of
RxPClk. The XRT79L74 device will compare the data on the Receive POS-
PHY Address Bus with the pre-programmed POS-PHY Address value (which
was loaded into the XRT79L74 device by writing the appropriate data into the
"Receive POS-PHY Interface - Receive Control Register - Byte 0" (Address =
0x0502). If these two values are identical and the "RxPENB*" input pin is
asserted, then the RxPPA output pin will be driven to the appropriate state
(based upon the RxFIFO fill-level). If these two values do not match, then the
Receive POS-PHY Interface block will continue to tri-state the "RxPPA" output
pin.
NOTE:
These input pins are only active if the XRT79L74 device has been
configured to operate in either the ATM UNI or PPP Modes. The user
should tie these input pins to GND if he/she wishes to operate the
XRT79L74 device in either the "Clear-Channel Framer" or "High-Speed
HDLC Controller" Modes.
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