XRT79L74 Datasheet, PDF(20/70 Page) Exar Corporation – 4

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XRT79L74 Datasheet, PDF (20/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

◁

XRT79L74

REV. P1.0.0

PIN #

NAME

TxUPrty/

TxPPrty

TxUEN/

TxPEN

PRELIMINARY

4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

TYPE

DESCRIPTION

I Transmit UTOPIA Data Bus - Parity Input/Transmit POS-PHY Interface - Par-

ity Input:

The function of this input pin depends upon whether the XRT79L74 has been

configured to operate in the ATM UNI or PPP Mode.

ATM UNI Mode - TxUPrty:

The ATM Layer processor will apply the parity value of the byte or word which is

being applied to the Transmit UTOPIA Data Bus (e.g., TxUData[7:0] or TxU-

Data[15:0]) inputs of the XRT79L74, respectively.

NOTE: This parity value should be computed based upon the odd-parity of the

data applied at the Transmit UTOPIA Data Bus.

The Transmit UTOPIA Interface block within the XRT79L74 will independently

compute an odd-parity value of each byte (or word) that it receives from the ATM

Layer processor and will compare it with the logic level of this input pin.

PPP Mode - TxPPrty:

The Link Layer Processor will apply the parity value of the byte or word which is

being applied to the Transmit POS-PHY Data Bus (e.g., TxPData[7:0] or TxP-

Data[15:0]) inputs of the XRT79L74, respectively.

NOTE: This parity value should be computed based upon the odd-parity of the

data applied to the Transmit POS-PHY Data Bus. The Transmit POS-

PHY Interface block within the XRT79L74 will independently compute an

odd-parity value of each byte (or word) that it receives from the Link

Layer processor and will compare it will the logic level of this input pin.

This input pin is only active if the user has configured the XRT79L74

device to operate in either the ATM UNI or the PPP Mode. The user

should tie this input pin to GND if he/she intends to operate the

XRT79L74 device in either the Clear-Channel Framer or High-Speed

HDLC Controller Modes.

I Transmit UTOPIA Interface Block - Write Enable/Transmit POS-PHY Inter-

face - Write Enable:

The exact function of this input pin depends upon whether the XRT79L74 device

has been configured to operate in the ATM UNI or PPP Mode.

ATM UNI Mode Operation - TxUENB* - Transmit UTOPIA Interface - Write

Enable Input pin:

This active-low signal, from the ATM Layer processor enables the data on the

Transmit UTOPIA Data Bus to be latched and written into the TxFIFO on the ris-

ing edge of TxUClk. When this signal is asserted (e.g., pulled to a logic "LOW"

level), then the contents of the byte or word that is present, on the Transmit UTO-

PIA Data Bus (TxUData[15:0]), will be latched into the Transmit UTOPIA Inter-

face block, on the rising edge of TxUClk. When this signal is negated, then the

Transmit UTOPIA Data bus inputs will be tri-stated.

PPP Mode Operation - TxPENB*

This active-low signal, from the Link Layer processor enables the data on the

Transmit POS-PHY Data Bus to latched and be written into the TxFIFO on the

rising edge of TxPClk. When this signal is asserted (e.g., pulled to a logic "LOW"

level), then the contents of the byte or word that is present, on the Transmit POS-

PHY Data Bus (TxPData[15:0]), will be latched into the Transmit POS-PHY Inter-

face block, on the rising edge of TxPClk.When this signal is negated, then the

Transmit POS-PHY Data bus inputs will be tri-stated.

NOTE: This input pin is only active if the XRT79L74 device has been configured

to operate in the ATM UNI or PPP Mode. The user should tie this input

pin to GND if he/she intends to operate the XRT79L74 device in either

the Clear-Channel Framer or High-Speed HDLC Controller Mode.

▷