XRT79L74 Datasheet, PDF (13/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74
REV. P1.0.0
PIN #
T3
M26
V5
P24
G1
C24
H4
C26
NAME
TxSer1/TxPOH1/
SendMSG1
TxSer2/TxPOH2/
SendMSG2
TxSer3/TxPOH3/
SendMSG3
TxSer4/TxPOH4/
SendMSG4
TxPOHFrame1
TxPOHFrame2
TxPOHFrame3
TxPOHFrame4
TYPE
I
I
I
I
O
O
O
O
DESCRIPTION
Transmit Payload Data Serial Input/Transmit PLCP Path Overhead Input/
Send HDLC Message Request Input:
The function of these input pins depend upon whether the XRT79L74 is config-
ured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Con-
troller Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxSer:
If the XRT79L74 is configured to operate in the Clear-Channel Framer mode,
then these input pins function as the Transmit Payload Data Serial Input pins. In
this case, the local terminal equipment is expected to apply all outbound data
which is intended to be carried via the DS3 or E3 payload bits to these input pins.
The Transmit Payload Data Input Interface will sample the data, residing at the
TxSer input pin, upon the rising edge of TxInClk.
ATM/PLCP Mode - TxPOH:
If the XRT79L74 is configured to operate in the ATM Mode, and if within the ATM
Mode, the chip is also configured to operate in the PLCP Mode, then these input
pins function as the Transmit PLCP Path Overhead Input Pins. In this mode, the
user can externally insert desired path overhead byte values into the outbound
PLCP frames.
The Transmit PLCP Path Overhead Input Pin (and Port) become active whenever
the user asserts the TxPOHIns input pins by pulling them "High". In this case,
the data, residing upon the TxPOH input pins will be sampled upon the rising
edge of the TxPOHClk signals.
NOTE: These input pins are inactive if the XRT79L74 is configured to operate in
the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - SendMSG:
If the XRT79L74 is configured to operate in the High-Speed HDLC Controller
Mode, then these input pins function as the Transmit HDLC Controller Input
Interface enable input pin.
If the user asserts these input pins by pulling them "High" then the Transmit
HDLC Controller Input Interface will proceed to latch the data, residing on the
TxHDLCDatn_[7:0] input pins, upon each rising edge of the TxHDLCClk signals.
All data that is latched into the Transmit HDLC Controller Input Interface for the
duration that the SendMSG input pin is "High" will be encapsulated into an HDLC
frame and ultimately transported via the payload bits of the outbound DS3 or E3
data stream.
If the user pulls these input pins "Low", then the Transmit HDLC Controller Input
Interface will cease latching the data, residing on the TxHDLCDatn_[7:0] bus.
NOTE: These input pins are inactive if the XRT79L74 has been configured to
operate in the PPP Mode.
Transmit PLCP Frame Path Overhead Byte Serial Input Port - Beginning of
Frame indicator:
These output pins, along with the TxPOH, TxPOHClk, and the TxPOHIns pins
comprise the Transmit PLCP Frame POH Byte Insertion serial input port. These
particular pins pulse "High" when the Transmit PLCP POH Byte Insertion serial
input port is expecting the first bit of the Z6 byte at the TxPOH input pins.
NOTE: These pins are only active if the XRT79L74 has been configured to
operate in the ATM/PLCP Mode.
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