XRT79L74 Datasheet, PDF (37/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74
REV. P1.0.0
PIN #
B12
A13
C13
NAME
RxUClk/
RxPClk
RxPERR
RxTSX/
RxPSOF
TYPE
I
O
O
DESCRIPTION
Receive UTOPIA Interface Clock Input/Receive POS-PHY Interface Clock
Input:
The function of this input pin depends upon whether the XRT79L74 is operating
in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClk:
The byte (or word) data, on the Receive UTOPIA Data bus (RxUData[15:0]) is
updated on the rising edge of this signal. The Receive UTOPIA Interface can
be clocked at rates up to 50 MHz.
PPP Mode - RxPClk:
This byte (or word) data, on the Receive POS-PHY Data Bus (RxPData[15:0]) is
updated on the rising edge of this signal. The Receive POS-PHY Interface can
be clocked at rates up to 50MHz.
NOTE: The user should tie this pin to GND if he/she wishes to operate the
XRT79L74 device in the Clear-Channel Framer or High-Speed HDLC
Controller Modes.
Receive POS-PHY Interface - Error Indicator:
This output pin indicates whether or not the Receive PPP Packet
Processor block has detect any of the following types of erred packets
within the incoming PPP Packet data-stream.
• Packets with FCS Errors
• Aborted Packets
• RUNT Packets
Anytime the Receive PPP Packet Processor block detects these types
of PPP Packets, then the XRT79L74 device will pulse this output pin
"high" coincident to whenever the Receive POS-PHY Interface block
outputs the very last byte or 16-bit word of the erred packet via the
"RxPData[15:0]" output pins.The XRT79L74 device will hold this output
pin "low" at all other times.
NOTE: This output pin is only valid if the XRT79L74 has been configured to
operate in the PPP Mode.
Receive - Start of Transfer/Receive - Start of PPP Packet in Chunk Mode:
The function of this output pin depends upon whether the XRT79L74 has been
configured to operate in the Packet Mode or Cell-Chunk Mode.
Packet Mode - RxTSX:
The XRT79L74 pulses this output pin "High" when an inband port address is
present on the RxPData[7:0] bus.
When this output pin is "High", the value of RxPData[7:0] is the address value of
the RxFIFO to be selected. Subsequent read operations, from RxPData[15:0]
will be from the RxFIFO corresponding to this inband address.
Chunk Mode - RxPSOF:
The XRT79L74 pulses this output pin "High" in order to indicate that the first
byte (or word) of a given Packet is placed on the RxPData[15:0] pins.
NOTE: This output pin is only active if the XRT79L74 has been configured to
operate in the PPP Mode.
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