XRT79L74 Datasheet, PDF (31/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74
REV. P1.0.0
PIN #
K1
L2
F24
H26
N3
J26
R4
M22
B1
D21
E4
B24
NAME
RxOHFrame1/
RxHDLCDat1_4
RxOHFrame2/
RxHDLCDat2_4
RxOHFrame3/
RxHDLCDat3_4
RxOHFrame4/
RxHDLCDat4_4
RxFrame1
RxFrame2
RxFrame3
RxFrame4
RxCellRxed1
RxCellRxed2
RxCellRxed3
RxCellRxed4
TYPE
O
O
O
O
0
O
O
O
O
O
O
O
DESCRIPTION
Receive Overhead Data Interface - Framing Pulse indicator/Receive HDLC
Controller Data Bus - Bit 4 output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHFrame:
These output pins pulse "High" whenever the Receive Overhead Data Output
Interface block outputs the first overhead bit of a new DS3 or E3 frame.
High-Speed HDLC Controller Mode - RxHDLCDat_4:
These output pins along with RxHDLCDatn_[3:0] and RxHDLCDatn_[7:5] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user’s
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
Receive Boundary of DS3 or E3 Frame Output indicator:
The function of these output pins depend upon whether or not the XRT79L74 is
operating in the Clear-Channel Framer/Nibble-Parallel Mode.
Clear-Channel Framer/Nibble-Parallel Mode:
The Receive Section of the XRT79L74 will pulse these output pins "High" for
one nibble period, when the Receive Payload Data Output interface block is
driving the very first nibble of a given DS3 or E3 frame, on the RxNibn[3:0] out-
put pins.
Clear-Channel Framer/Serial Mode:
The Receive Section of the XRT79L74 will pulse these output pins "High" for
one bit period, when the Receive Payload Data Output interface block is driving
the very first bit of a given DS3 or E3 frame, on the RxSer output pin.
All Other Modes:
The Receive Section of the XRT79L74 will pulse these output pins "High" when
the Receive DS3/E3 Framer block is processing the first bit within a new DS3 or
E3 frame.
Receive Cell Processor - Cell Received Indicator:
These output pins pulse "High" each time the Receive Cell Processor receives
a new cell from the Receive PLCP Processor or the Receive DS3/E3 Framer
block.
These output pins are only active if the XRT79L74 has been configured to oper-
ate in the ATM UNI Mode.
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