XRT79L74 Datasheet, PDF (30/70 Pages) Exar Corporation – 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PIN #
J4
F26
K5
G23
J3
E26
K4
G24
J5
F25
L1
G22
NAME
RxOHEnable1/
RxHDLCDat1_5
RxOHEnable2/
RxHDLCDat2_5
RxOHEnable3/
RxHDLCDat3_5
RxOHEnable4/
RxHDLCDat4_5
RxOH1/
RxHDLCDat1_6
RxOH2/
RxHDLCDat2_6
RxOH3/
RxHDLCDat3_6
RxOH4/
RxHDLCDat4_6
RxOHClk1/
RxHDLCClk1
RxOHClk2/
RxHDLCClk2
RxOHClk3/
RxHDLCClk3
RxOHClk4/
RxHDLCClk4
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
Receive Overhead Data Output Interface - Enable Output/Receive HDLC
Controller Data Bus - Bit 5 output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHEnable:
The XRT79L74 will assert these output signals for one RxOHClk period when it
is safe for the local terminal equipment to sample the data on the RxOH output
pins.
High-Speed HDLC Controller Mode - RxHDLCDat_5:
These output pins along with RxHDLCDatn_[4:0], RxHDLCDatn_6 and
RxHDLCDatn_7 functions as the Receive HDLC Controller byte wide output
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the RxHDLCClk output
signals. Hence, the user’s local terminal equipment should be designed/config-
ured to sample this data upon the falling edge of the RxHDLCClk output clock
signals.
Receive Overhead Data Output Interface - output/Receive HDLC Controller
Data Bus - Bit 6 output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOH:
All overhead bits, which are received via the Receive Section of the XRT79L74
will be output via these output pins, upon the rising edge of RxOHClk.
High-Speed HDLC Controller Mode - RxHDLCDat_6:
These output pins along with RxHDLCDatn_[5:0] and RxHDLCDatn_7 functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signals. Hence, the user’s local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signals.
Receive Overhead Data Output Interface - clock/Receive HDLC Controller -
Clock output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHClk:
The XRT79L74 will output the overhead bits within the incoming DS3 or E3
frames via the RxOH output pins, upon the falling edge of these clock signals.
As a consequence, the user’s local terminal equipment should use the rising
edge of these clock signals to sample the data on both the RxOH and RxO-
HFrame output pins.
NOTE: These clock signals are always active.
High-Speed HDLC Controller Mode - RxHDLCClk:
These output pins function as the Receive HDLC Controller Data bus clock out-
put. The Receive HDLC Controller block outputs the contents of all received
HDLC frames via the Receive HDLC Controller Data bus (RxHDLCDatn_[7:0])
upon the rising edge of these clock signals. Hence, the user’s local terminal
equipment should be designed/configured to sample these data upon the falling
edge of these clock signals.
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