XR16M598 Datasheet, PDF (37/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO

XR16M598
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load. Table 15 below shows the selections.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software compatibility.
• Logic 0 = Set DMA to mode 0 (default).
• Logic 1 = Set DMA to mode 1.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
• Logic 0 = No receive FIFO reset (default).
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
TABLE 15: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCR
BIT-7
0
0
1
1
FCR
BIT-6
0
1
0
1
FCR
BIT-5
0
0
1
1
FCR
BIT-4
0
1
0
1
RECEIVE TRIGGER
TRANSMIT
LEVEL
TRIGGER LEVEL
COMPATIBILITY
1(default)
4
8
14
1(default)
4
8
14
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
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