XR16M598 Datasheet, PDF (15/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO

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XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
TABLE 6: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
CH0 0x00 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH0 0x00 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x10 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x10 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x20 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x20 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x30 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x30 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH4 0x40 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH4 0x40 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH5 0x50 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH5 0x50 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH6 0x60 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH6 0x60 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH7 0x70 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH7 0x70 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
THRRHR1
2.10 Auto RTS/DTR Hardware Flow Control Operation
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR#
output pin is used to request remote unit to suspend/resume data transmission. The flow control features are
individually selected to fit specific application requirement (see Figure 9):
• Select RTS (and CTS) or DTR (and DSR) through MCR bit-2.
• Enable auto RTS/DTR flow control using EFR bit-6.
• The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level (See Table 15). The RTS# output pin will be asserted (LOW) again after the FIFO is unloaded to the next
trigger level below the programmed trigger level.
However, even under these conditions, the 598 will continue to accept data until the receive FIFO is full if the
remote UART transmitter continues to send data.
• If used, enable RTS/DTR interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR bit-5 will be set to 1.
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