XR16M598 Datasheet, PDF (24/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO

XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.0
3.1 DEVICE CONFIGURATION REGISTER SET
The device configuration registers are directly accessible from the bus. This provides easy programming of
general operating parameters to the 598 UART and for monitoring the status of various functions. The device
configuration registers are mapped onto address 0x80-8F as shown on the register map in Table 9 and
Figure 12. These registers provide global controls and status of all 8 channel UARTs that include interrupt
status, 16-bit general purpose timer control and status, 4X or 8X or 16X sampling clock, sleep mode control,
soft-reset control, simultaneous UART initialization, and device identification and revision.
TABLE 8: XR16M598 REGISTER SETS
ADDRESS [A7:A0]
UART CHANNEL SPACE
REFERENCE
COMMENT
0x00 - 0x0F
UART channel 0 Registers
(Table 12 & 13)
0x10 - 0x1F
UART channel 1 Registers
(Table 12 & 13)
0x20 - 0x2F
UART channel 2 Registers
(Table 12 & 13)
0x30 - 0x3F
0x40 - 0x4F
UART channel 3 Registers
UART channel 4 Registers
(Table 12 & 13) _{First 8 registers are 16550 compatible}
(Table 12 & 13)
0x50 - 0x5F
UART channel 5 Registers
(Table 12 & 13)
0x60 - 0x6F
UART channel 6 Registers
(Table 12 & 13)
0x70 - 0x7F
UART channel 7 Registers
(Table 12 & 13)
0x80 - 0x8F
Device Configuration Registers
(Table 9)
Interrupt registers and global controls
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