XR16M598 Datasheet, PDF (14/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO

XR16M598
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
FIGURE 7. RECEIVER OPERATION IN NON-FIFO MODE
REV. 1.0.0
16X or 8X or 4X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
R X FIFO 1
FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X or 4X Clock
16 bytes by 11-bit
wide
FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
Receive
Data
Data Bit
Validation
Receive Data Characters
Example:
- RX FIFO trigger level selected at 8 bytes
(See Note Below)
Data falls to 4
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO Trigger=8
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to 14
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
2.9 THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 6 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
14