XR16M598 Datasheet, PDF (19/58 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO

XR16M598
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
2.13 Auto RS-485 Half-duplex Control
The auto RS-485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. It also changes the behavior of the transmit empty interrupt (see Table 3). It asserts RTS# or DTR#
(LOW) after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has
been transmitted. This helps in turning around the transceiver to receive the remote station’s response. The
delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network
before switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal
degradation. When the host is ready to transmit next polling data packet again, it only has to load data bytes to
the transmit FIFO. The transmitter automatically de-asserts RTS# or DTR# output (HIGH) prior to sending the
data. The auto RS-485 half-duplex direction control also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
2.13.1 Normal Multidrop Mode
Normal multidrop mode is enabled when MSR bit-0 = 1 and EFR bit-5 = 0 (Special Character Detect disabled).
The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to anything. If the address does not match its slave address, then the receiver
should be disabled.
2.13.2 Auto Address Detection
Auto address detection mode is enabled when MSR bit-0 = 1 and EFR bit-5 = 1. The desired slave address
will need to be written into the XOFF2 register. The receiver will try to detect an address byte that matches the
porgrammed character in the XOFF2 register. If the received byte is a data byte or an address byte that does
not match the programmed character in the XOFF2 register, the receiver will discard these data. Upon
receiving an address byte that matches the XOFF2 character, the receiver will be automatically enabled if not
already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates an LSR interrupt. The receiver will then receive the subsequent
data. If another address byte is received and this address does not match the programmed XOFF2 character,
then the receiver will automatically be disabled and the address byte is ignored. If the address byte matches
XOFF2, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit.
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