XR88C92 Datasheet, PDF (21/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
bit in this register is also a “1”, the -INT output will be
asserted. If the corresponding bit in this register is a
zero, the state of the bit in the interrupt status register
has no effect on the -INT output. Note that the interrupt
mask register does not have any effect on the program-
mable interrupt outputs OP7 through OP3 or the value
read from the interrupt status register.
0 = Interrupt output (-INT) disabled (default)
1 = Enable interrupt output for the event controlled by the
corresponding bit in ISR.
COUNTER / TIMER REGISTERS
The Preload value Upper (CTPU) and Lower (CTPL)
registers hold the most-significant byte and the least-
significant byte, respectively, of the value to be used by
the C/T (in both counter and timer modes). The C/T
Upper (CUR) and Lower Registers (CLR) give the
current value of the C/T, at the time they are read. In the
counter mode, the CUR and CLR should only be read
when the counter is stopped. Upon receiving a start
command after a stop command, the counter starts a
fresh cycle and begins counting down from the original
(preload) value written to CTPU and CTPL. Also chang-
ing the value of these registers does not take effect till
the current cycle is stopped and a subsequent start
command is issued.
In the timer mode, the CUR and CLR registers cannot
be read by the CPU. A stop command will not stop the
timer, but will only clear the counter ready status bit in
ISR (bit-3). Changing the value of the CTPU and CTPL
registers when the timer is running will change the
waveform after the current half-period of the square
wave. For more details, see the Counter/Timer section.
GENERAL PURPOSE REGISTER (GPR)
This is a general purpose scratchpad register which can
be used to store and retrieve one byte of user
infomation.
INPUT PORT REGISTER - Read Only
The current state of the multi-purpose inputs (IP0-IP6)
can be read via this register.
IPR Bit 0-6:
0 = Inputs are in low state.
1 = Inputs are in high state.
IPR Bit-7:
Not used and is set to “0”.
OUTPUT PORT CONFIGURATION REGISTER
(OPCR) - Write Only
This register selects following options for the multi-
purpose outputs OP2 to OP7.4Alternate functions of
OP1 and OP0 are controlled by the mode registers, not
the OPCR. MR1A Bit-7 and MR2A Bit-5 control OP0.
MR1B Bit-7 and MR2B Bit-5 control OP1. For more
details on these, see 'Multi-purpose Outputs' on page 8.
OP2 Output Select
Bit-1 Bit-0
00
Controlled by SOPR and ROPR
(default)
01
TxAClk16-Transmit A 16X clock
10
TxAClk1-Transmit A 1X clock
11
RxAClk1- Receive A 1X clock
OP3 Output Select
Bit-3 Bit-2
00
Controlled by SOPR and ROPR
(default)
01
C/T Output
10
TxBClk1-Transmit B 1X clock
11
RxBClk1- Receive B 1X clock
If OP3 is to be used for the timer output (a square wave
of the programmed frequency), program the counter/
timer for timer mode (ACR Bit-6 = 1), initialize the
counter/timer pre-load registers (CTPU and CTPL), and
read the 'Start C/T Command Register' (STCR) before
setting OPCR Bits 3-2 = 01. In the counter mode, the
output remains high until the terminal count is reached,
at which time it goes low. The output becomes high again
when the counter is stopped by a stop counter com-
mand.
OP4 output select (Bit 4):
0 = Controlled by SOPR and ROPR (default)
1 = -RxARDY which is the complement of ISR bit-1
OP5 output select (Bit 5):
0 = Controlled by SOPR and ROPR (default)
1 = -RxBRDY which is the complement of ISR bit-5
OP6 output select (Bit 6):
0 = Controlled by SOPR and ROPR (default)
1 = -TxARDY which is the complement of ISR bit-0
OP7 output select (Bit 7):
0 = Controlled by SOPR and ROPR (default)
1 = -TxBRDY which is the complement of ISR bit-4
Rev. 1.31
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