XR88C92 Datasheet, PDF (12/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
station. When the slave stations' receivers detect an
address character, each receiver notifies its respective
CPU by setting receiver ready (-RXRDY) and generating
an interrupt, if programmed to do so. Each slave station
CPU then compares the received address to its station
address and enables its receiver if the addresses
match. Slave stations that are not addressed, continue
monitoring the data stream for the next address charac-
ter. An address character marks the beginning of a new
block of data. After receiving a block of data, the slave
stations CPU may disable the channel receiver and re-
initiate the process.
A transmitted character from the master station con-
sists of a start bit, the programmed number of data bits,
an address/data (A/D) bit tag (replacing the parity bit
used in normal operation), and the programmed number
of stop bits. The A/D tag indicates to the slave stations
channel whether the character should be interpreted as
an address character or a data character. The charac-
ter is interpreted as an address character if the A/D tag
is set to a '1' or interpreted as a data character if it is set
to a '0'. The polarity of the transmitted A/D tag is selected
by programming MR1A, MR1B bit-2 to a '1' for an
address character and to a '0' for data characters. Users
should program the mode register prior to loading the
corresponding data or address characters into the
transmit buffer.
As a slave station, the XR88C92/192 receiver continu-
ously monitors the received data stream regardless of
whether it is enabled or disabled. If the receiver is
disabled, it sets the receiver ready status bit and loads
the character into the FIFO receive holding register
stack provided the received A/D tag is a '1' (address
tag). The received character is discarded if the received
address/data bit is a '0' (data tag). If the receiver is
enabled, all received characters are transferred to the
CPU during read operations. In either case, the data
bits are loaded into the data portion of the FIFO stack
while the address/data bit is loaded into the status
portion of the FIFO stack normally used for parity error
(SRA, SRB bit-5). Framing error, overrun error, and
break-detection operate normally regardless of whether
the receiver is enabled or disabled. The address/data
(A/D) tag takes the place of the parity bit and parity is
neither calculated nor checked for characters in this
mode.
Extra Storage For The A/D Tag: The unique feature of
XR88C92/192 is that the the user need not wait at all in
order to change the A/D tag from address to data
(whereas in the case of SC26C92, a wait of at least 2 bit-
times is required before changing the A/D tag). This
allows the user to possibly load the entire polling packet
data to the TX FIFO.
WATCHDOG TIMER
Each of the two receivers (channel A & B) has its own
'watchdog timer' which is separate from and indepen-
dent of the Counter/Timer. The watchdog timer is used
to generate a receive ready time-out interrupt. When it
is enabled, a counter is started everytime a character is
transferred from the receive shift register to the receive
FIFO and times out after 64 bit-times, at which point it
will generate a receive interrupt. This is a useful feature
especially when the incoming data is not a continous
stream of data. For example, if RX trigger levels are used
and the last set of characters is smaller than the trigger
level, a receive time-out interrupt is generated instead of
a regular receive interrupt. The watchdog timer, how-
ever, is not accurate as it uses the incoming data for its
timing. For more accurate timing, the time-out mode in
Counter/Timer should be used (see below).
COUNTER/TIMER
The 16-bit counter/timer (C/T) can operate in a counter
mode or a timer mode. In either mode, users can
program the C/T input clock source to come from
several sources (see ACR bits 6:4) and program the
C/T output to appear on output port pin OP3 (see OPCR
bits 3:2). The value (pre-load value) stored in the
concatenation of the C/T upper register (CTPU, ad-
dress 0x6) and the C/T lower register (CTPL, address
0x7) can be from 0x0001 through 0xFFFF and can be
changed at any time. At power-up and after reset, the C/
T operates in counter mode.
COUNTER MODE
In counter mode, the CPU can start and stop the C/T.
This mode allows the C/T to function as a system
stopwatch or a real-time single interrupt generator. In
this mode, the C/T counts down from the pre-load value
using the programmed counter clock source. When a
read at the start counter command register (address
0xE) is performed, the counter is initialized to the pre-
load value and begins a countdown sequence. When
the counter counts from 0x0001 to 0x0000 (terminal
count), the C/T-ready bit in the interrupt status register
(ISR Bit-3) is set.
3
Rev. 1.31
12