XR88C92 Datasheet, PDF (14/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
address 0xE) is read, the C/T terminates the current
countdown sequence and sets its output to a '1' (OP3
can be programmed to show this output). The C/T is
then initialized to the pre-load value, and begins a new
countdown sequence. When the terminal count is
reached (0x0000), the C/T sets its output to a '0'. Then,
it gets re-initialized to the pre-load value and repeats the
countdown sequence. See Figure 2 for the resulting
waveform.
The timer sets the C/T-ready bit in the interrupt status
register (ISR Bit-3) every other time it reaches the
terminal count (at every rising edge of the output). Users
can program the timer to generate an interrupt request
for this condition (every second countdown cycle) on
the -INT output. If the CPU changes the pre-load value,
the timer will not recognize the new value until either
(a) it reaches the next terminal count and is reinitialized
automatically, or
(b) it is forced to re-initialize by a start command.
When a read at the stop counter command address is
performed, the timer clears ISR Bit-3 but does not stop.
Because in timer mode the C/T runs continuously, it
should be completely configured (pre-load value loaded
and start counter command issued) before program-
ming the timer output to appear on OP3.
OTHER PROGRAMMING REMARKS
The contents of internal registers should not be changed
during receiver/transmitter operation as certain
changes can produce undesired results. For example,
changing the number of bits per character while the
transmitter is active will result in transmitting an incorrect
character. The contents of the clock-select register
(CSR) and ACR Bit-7 should only be changed after the
receiver(s) and transmitter(s) have been issued soft-
ware RX and TX reset commands. Similarly, changes
to the auxiliary control register (ACR Bits 4-6) should
only be made while the counter/timer (C/T) is not used.
The mode registers of each channel MR0, MR1 and
MR2 are accessed via an auxiliary pointer. The pointer
is set to mode register one (MR1) by RESET. It can be
set to MR0 or MR1 by issuing a “reset pointer” command
(0xB0 or 0x10 respectively) via the channel's command
register. Any read or write of the mode register switches
the pointer to next mode register. All accesses subse-
quent to reading/writing MR1 will address MR2 unless
the pointer is reset to MR0 or MR1 as described above.
The mode, command, clock-select, and status registers
are duplicated for each channel to allow independent
operation and control (except that both channels are
restricted to baud rates that are in the same set).
INTERNAL REGISTER DESCRIPTIONS
A3 A2 A1 A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
READ Operation
Mode Register A (MR0A, MR1A, MR2A)
Status Register A (SRA)
Reserved
Receiver Buffer A (RXA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Register (CUR)
Counter/Timer Lower Register (CLR)
Mode Register B (MR0B, MR1B, MR2B)
Status Register B (SRB)
Reserved
Receiver Buffer B (RXB)
General Purpose Register (GPR)
Input Port Register (IPR)
Start C/T Command (STCR)
Stop C/T Command (SPCR)
WRITE Operation
Mode Register A (MR0A, MR1A, MR2A)
Clock-Select Register A (CSRA)
Command Register A (CRA)
Transmitter Buffer A (TXA)
Auxiliary Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Preload value Upper Register (CTPU)
C/T Preload value Lower Register (CTPL)
Mode Register B (MR0B, MR1B, MR2B)
Clock-Select Register B (CSRB)
Command Register B (CRB)
Transmitter Buffer B (TXB)
General Purpose Register (GPR)
Output Port Configuration Register (OPCR)
Set Output Port Register (SOPR)
Reset Output Port Register (ROPR)
Rev. 1.31
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