XR88C92 Datasheet, PDF (18/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
Baud Rate Table for a 3.6864MHz clock. Data rates would double for a 7.3728MHz clock.
MR0 Bits
2,0=0
MR0 Bit-0=1
(extended table 1)
MR0 Bit-2=1
(extended table 2)
CSRA, CSRB SET-1
Bits 7:4 or
ACR
Bits 3:0
Bit-7=0
SET-2
ACR
Bit-7=1
SET-1
ACR
Bit-7=0
SET-2
ACR
Bit-7=1
SET-1
ACR
Bit-7=0
SET-2
ACR
Bit-7=1
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110*
1111*
50
110
134.5
200
300
600
1200
1050
2400
4800
7200
9600
38.4k
Timer
75
110
134.5
150
300
600
1200
2000
2400
4800
1800
9600
19.2k
Timer
300
110
134.5
1200
1800
3600
7200
1050
14.4k
28.8k
7200
57.6k
230.4k
Timer
450
110
134.5
900
1800
3600
7200
2000
14.4k
28.8k
1800
57.6k
115.2k
Timer
4800
880
1076
19.2k
28.8k
57.6k
115.2k
1050
57.6k
4800
57.6k
9600
38.4k
Timer
7200
880
1076
14.4k
28.8k
57.6k
115.2k
2000
57.6k
4800
14.4k
9600
19.2k
Timer
IP3-16X (CSRA 3:0), IP4-16X (CSRA 7:4), IP5-16X (CSRB 3:0), IP6-16X (CSRB 7:4)
IP3-1X (CSRA 3:0), IP4-1X (CSRA 7:4), IP5-1X (CSRB 3:0), IP6-1X (CSRB 7:4)
* Baud Rate is independent of MR0 bit-0 & bit-2 and ACR bit-7 settings.
CLOCK SELECT REGISTER (CSRA, CSRB)
Transmit / Receive baud rates for channels A, B can be
selected via this register.
CSRA, CSRB Bits 3-0.
Transmit clock select(see baud rate table).
CSRA, CSRB Bits 7-4.
Receive clock select (see baud rate table).
COMMAND REGISTER (CRA, CRB)
CRA, CRB register is used to supply commands to A,
B channels respectively. Multiple commands can be
specified in a single write to CRA, CRB as long as
commands are non-conflicting.
CRA, CRB Bits 1-0: Receiver Commands.
0 0 = No Action, Stays in Present Mode (default)
0 1 = Receiver Enabled
1 0 = Receiver Disabled
1 1 = Don’t Use
CRA, CRB Bits 3-2: Transmitter Commands.
0 0 = No Action, Stays in Present Mode (default)
0 1 = Transmitter Enabled
1 0 = Transmitter Disabled
1 1 = Don’t Use
CRA, CRB Bits 7-4: Miscellaneous Commands.
0 0 0 0 = No Command (default).
0 0 0 1 = Reset MR Pointer to MR1.
0 0 1 0 = Reset Receiver. Receiver is disabled and
FIFO is flushed.
0 0 1 1 = Reset Transmitter. Transmitter is disabled
and FIFO is flushed.
0 1 0 0 = Reset Error Status. Clears channel A/B,
break, parity, and over-run error bits in the
status register.
0 1 0 1 = Reset Channel's Break-Change Interrupt.
Clears channel A/B break detect change bit
in the interrupt status register (ISR bit-2 for
channel A and ISR bit-6 for channel B).
Rev. 1.31
18