XR88C92 Datasheet, PDF (17/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
Register) to reset the pointer to MR0 or MR1.
MR2A, MR2B Bits 3-0: Stop bit length.
0000 = 0.563 (default)
1000 = 1.563
0001 = 0.625
1001 = 1.625
0010 = 0.688
1010 = 1.688
0011 = 0.750
1011 = 1.750
0100 = 0.813
1100 = 1.813
0101 = 0.875
1101 = 1.875
0110 = 0.938
1110 = 1.938
0111 = 1.000
1111 = 2.000
MR2A, MR2B Bit-4: Auto CTS Flow control.
0 = No Auto CTS flow control (default)
1 = Auto CTS flow control enabled
MR2A, MR2B Bit-5: Auto Transmit RTS control.
0 = No Auto TX RTS control (default)
1 = Auto Transmit RTS function enabled
The output OP0 (OP1) serves as the -RTS signal for
channel A (channel B). Note that only one of MR1 bit-
7 or MR2 bit-5 should be set to '1'.
MR2A, MR2B Bit 7-6: Loopback mode select.
0 0 = No loopback (default)
0 1 = Automatic Echo
1 0 = Local Loopback
1 1 = Remote Loopback
STATUS REGISTER (SRA, SRB)
SRA, SRB Bit-0: Receive Ready.
This bit indicates that one or more character(s) has
been received and is waiting in the FIFO for the CPU to
read them. It is set when the first character is transferred
from the receive shift register to the empty FIFO, and
cleared when the CPU reads the receiver buffer and
there are no more characters in the FIFO after the read.
SRA, SRB Bit-1: Receive FIFO Full.
This bit is set when a character is transferred from the
receive shift register to the receiver FIFO and the
transfer fills the FIFO. All eight (or 16 in XR88C192)
FIFO locations are occupied. It is cleared when the CPU
reads the receiver buffer, unless another character is
in the receive shift register waiting for an empty FIFO
location.
SRA, SRB Bit-2: Transmit Ready.
This bit (when set) indicates that the transmit FIFO is
not full. Transmitter ready bit is set when the transmit
FIFO has at least one empty location. This bit is cleared
when the transmit FIFO is full.
SRA, SRB Bit-3: Transmit Empty.
This bit will be set when the channel's transmitter is
empty. It indicates that both the transmit FIFO and the
transmit shift register are empty. It is set after transmis-
sion of the last stop bit of the last character in the TX
FIFO. It is cleared when the CPU loads a character into
the transmit FIFO or when the transmitter is disabled.
SRA, SRB Bit-4: Overrun Error.
This bit is set when one or more characters in the
received data stream have been lost. It is set on receipt
of a valid start bit when the FIFO is full and a character
is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the character
in the receive shift register (and its break detect, parity
error, and framing error status, if any) is overwritten. A
reset error status command clears this bit.
SRA, SRB Bit-5: Parity Error.
This bit is set when the “with parity” or “force parity”
mode is programmed by MR1A (or MR1B) and an
incoming character is received with incorrect parity. In
the Multidrop mode, the parity error bit position stores
the received address/data tag. This bit is valid only when
the RxRDY bit is set (SRA, SRB bit-0 = 1).
SRA, SRB Bit-6: Framing Error.
This bit is set when a stop bit was not detected when the
corresponding data character in the FIFO was re-
ceived. The stop bit check is made in the middle of the
first stop bit position. At least one bit in the received
character (data or parity) must have been a “1” to signal
a framing error. After a framing error, the receiver does
not wait for the line to return to the marking state (high).
If the line remains low for 1/2 a bit time after the stop bit
sample (that is, the nominal end of the first stop bit), the
receiver treats it as the beginning of a new start bit.This
bit is valid only when the RxRDY bit is set (SRA, SRB
Bit-0 = 1).
SRA, SRB Bit-7: Received Break.
This bit indicates a character with all data bits being zero
has been received without a stop bit. This bit is valid only
when the RxRDY bit is set (SRA, SRB Bit-0 = 1). Only
a single FIFO position is occupied when a break is
received; for longer break signals, additional entries to
the FIFO are inhibited until the channel A/B receiver
serial data input line returns to the marking state. The
break-detect circuitry can detect a break that starts in
the middle of a received character however, the break
condition must persist completely through the end of
the current character and the next character time to be
recognized as a break signal.
Rev. 1.31
17