RFM92 Datasheet, PDF (90/126 Pages) List of Unclassifed Manufacturers – Low Power Long Range Transceiver Module

RFM92W/93W V3.0
Address
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Register Name
FSK/OOK Mode
RegAfcMsb
RegAfcLsb
RegFeiMsb
RegFeiLsb
RegPreambleDe-
tect
RegRxTimeout1
LoRa^TM Mode
RegRssiValue
RegHopChannel
RegModemConfig
1
RegModemConfig
2
RegSymbTimeout
Lsb
RegPreambleMsb
RegRxTimeout2 RegPreambleLsb
0x22
0x23
0x24
RegRxTimeout3
RegRxDelay
RegOsc
RegPay-
loadLength
RegMaxPayloadL
ength
RegHopPeriod
0x25
0x26
0x27
0x28-
0x2F
0x30
0x31
0x32
RegPreambleMsb
RegPreambleLsb
RegSyncConfig
RegSyncValue1-8
RegPacketConfig1
RegPacketConfig2
RegPayloadLength
RegFifoRxByteAd
dr
RESERVED
Reset
(POR)
0x00
0x00
0x00
Default
(FSK)
n/a
n/a
0x08
0x00
0x74
0x40
0x64
0x00
0x00
0x00
0x00
0x00
0x08
0x01
0xFF
0x05
0x00
0x00
n/a
0x03
0x93
0x55
0x01
0x90
0x40
0x40
Description
FSK Mode
Frequency correction value of
the AFC
LoRa^TM Mode
Current RSSI
FHSS start channel
Value of the calculated
frequency error
Modem PHY config 1
Modem PHY config 2
Settings of the Preamble
Detector
Timeout Rx request and RSSI
Timeout RSSI and Pay-
loadReady
Timeout RSSI and SyncAd-
dress
Delay between Rx cycles
RC Oscillators Settings, CLK-
OUT frequency
Preamble length, MSB
Preamble length, LSB
Sync Word Recognition control
Receiver timeout value
Size of preamble
LoRaTM payload length
LoRaTM maximum pay-
load length
FHSS Hop period
Address of last byte
written in FIFO
LoRa^TM rx data pointer
Sync Word bytes, 1 through 8
Packet mode settings
Packet mode settings
RESERVED
Payload length setting
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
RegNodeAdrs
RegBroadcastAdrs
RegFifoThresh
RegSeqConfig1
RegSeqConfig2
RegTimerResol
RegTimer1Coef
RegTimer2Coef
RegImageCal
RESERVED
RegTemp
RegLowBat
RegIrqFlags1
RegIrqFlags2
RegDioMapping1
RegDioMapping2
0x00
0x00
0x0F
0x8F
0x00
0x00
0x00
0xF5
0x20
0x82
0x02
-
0x02
0x80
0x40
0x00
0x00
Node address
Broadcast address
Fifo threshold, Tx start condi-
tion
Top level Sequencer settings
Top level Sequencer settings
Timer 1 and 2 resolution control
Timer 1 setting
Timer 2 setting
Image calibration engine con-
trol
RESERVED
Temperature Sensor value
Low Battery Indicator Settings
Status register: PLL Lock state,
Timeout, RSSI
Status register: FIFO handling
flags, Low Battery
Mapping of pins DIO0 to DIO3
Mapping of pins DIO4 and DIO5, ClkOut frequency
Page 90
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