RFM92 Datasheet, PDF (78/126 Pages) List of Unclassifed Manufacturers – Low Power Long Range Transceiver Module

RFM92W/93W V3.0
5. RFM92W/93W Analog & RF Frontend
Electronics
5.1. Power Supply Strategy
The RFM92W/93W employs an internal voltage regulation scheme which provides stable operating voltage, and hence
device characteristics, over the full industrial temperature and operating voltage range. This includes up to +17 dBm of RF
output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.
The RFM92W/93W can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling
capacitors should be connected, as suggested in the reference design of the applications Section of this document, on
VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators.
5.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage
dropping below a programmable threshold that is adjustable through the register RegLowBat. The interrupt signal can be
mapped to any of the DIO pins by programming RegDioMapping.
5.3. Frequency Synthesis
5.3.1. Crystal Oscillator
The crystal oscillator is the main timing reference of the RFM92W/93W. It is used as the reference for the PLL’s
frequency synthesis and as the clock signal for all digital processing.
The crystal oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal reference used, for
more information on the electrical specification of the crystal see Section 2.3. The crystal connects to the Pierce oscillator
of pins XTA and XTB. The RFM92W/93W optimizes the startup time and automatically triggers the PLL when the
oscillator signal is stable.
Optionally, an external clock can be used to replace the crystal oscillator. This typically takes the form of a tight tolerance
temperature compensated crystal oscillator (TCXO). When using an external clock source the bit TcxoInputOn of register
RegTcxo should be set to 1 and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, C_D.
XTA
XTB
TCXO
32 MHz
NC
OP
Vcc
GND
Vcc
CD
Figure 39. TCXO Connection
Page 78
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