SEG04G72B1BC2MT-30R Datasheet, PDF (9/16 Pages) List of Unclassifed Manufacturers – 4GB DDR2 . SDRAM registered SO-RDIMM

preliminary Data Sheet
Rev.0.9 07.01.2013
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time CL = 5
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
SYMBOL
t_CK (5)
t_CK (4)
t_CK (3)
t_CH
t_CL
t_HP
Access window (output) of DQS
from CK/CK#
t_AC
Data-out high-impedance
window from CK/CK#
t_HZ
Data-out low-impedance window
from CK/CK#
t_LZ
DQ and DM input setup time
relative to DQS
t_DS
DQ and DM input hold time
relative to DQS
DQ and DM input pulse width
( for each input )
Data hold skew factor
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
Data valid output window
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS –DQ skew, DQS to last DQ
valid, per group, per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write preamble setup time
DQS write postamble
Positive DQS latching edge to
associated clock edge
Write command to first DQS
latching transition
Address and control input pulse
width ( for each input )
Address and control input setup
time
t_DH
t_DIPW
t_QHS
t_QH
t_DVW
t_DQSH
t_DQSL
t_DSS
t_DSH
t_DQSQ
t_RPRE
t_RPST
t_WPRE
t_WPRES
t_WPST
t_DQSS
t_IPW
t_IS
5300-555
MIN
MAX
3.0
8.0
3.75
8.0
5.0
8.0
0.45
0.55
0.45
0.55
min
(tCH, tCL)
-0.45 +0.45
-0.45
(=tAC min)
+0.45
(=tAC max)
+0.45
(=tAC max)
0.10
Unit
ns
ns
ns
tCK
tCK
ps
ns
ns
ns
ns
0.30
ns
0.35
tCK
0.34
ns
tHP - tQHS
ns
tQH - tDQSQ
ns
0.35
tCK
0.35
tCK
0.2
tCK
0.2
tCK
0.24
ns
0.9
0.4
0.35
0
0.4
1.1
tCK
0.6
tCK
tCK
ns
0.6
tCK
- 0.25 + 0.25 tCK
WL-
tDQSS
WL+
tDQSS
tCK
0.6
tCK
0.4
ns
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 9
of 16