SEG04G72B1BC2MT-30R Datasheet, PDF (12/16 Pages) List of Unclassifed Manufacturers – 4GB DDR2 . SDRAM registered SO-RDIMM

preliminary Data Sheet
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
0 NUMBER OF SPD BYTES USED
1 TOTAL NUMBER OF BYTES IN SPD DEVICE
2 FUNDAMENTAL MEMORY TYPE
3 NUMBER OF ROW ADDRESSES ON ASSEMBLY
4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
5 DIMM HIGHT AND MODULE RANKS
6 MODULE DATA WIDTH
7 RESERVED
8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ)
9
SDRAM CYCLE TIME, (tCK ) [max CL]
CAS LATENCY = 5 (5300), CL = 4 (4200)
10
SDRAM ACCESS FROM CLOCK, (tAC) [max CL]
CAS LATENCY = 5 (5300); CL = 4 (4200)
11 MODULE CONFIGURATION TYPE
12 REFRESH RATE / TYPE
13 SDRAM DEVICE WIDTH (PRIMARY SDRAM)
14 ERROR- CHECKING SDRAM DATA WIDTH
15
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
16 BURST LENGTHS SUPPORTED
17 NUMBER OF BANKS ON SDRAM DEVICE
18 CAS LATENCIES SUPPORTED
19 MODULE THICKNESS
20 DDR2 DIMM TYPE
21 SDRAM MODULE ATTRIBUTES
22 SDRAM DEVICE ATTRIBUTES: Weak Driver and 50 ODT
23
SDRAM CYCLE TIME, (tCK) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
24
SDRAM ACCESS FROM CK, (tAC) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
25
SDRAM CYCLE TIME, (tCK) [max CL – 2]
CAS LATENCY = 3 (5300)
26
SDRAM ACCESS FROM CK, (tAC) [max CL – 2]
CAS LATENCY = 3 (5300)
27 MINIMUM ROW PRECHARGE TIME, (tRP)
28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)
29 MINIMUM RAS# TO CAS# DELAY, (tRCD)
30 MINIMUM RAS# PULSE WIDTH, (tRAS)
31 MODULE BANK DENSITY
Rev.0.9 07.01.2013
5300-555
0x80
0x08
0x08
0x0F
0x0A
0x61
0x48
0x00
0x05
0x30
0x45
0x02
0x82
0x08
0x08
0x00
0x0C
0x08
0x38
0x01
0x07
0x04
0x03
0x3D
0x45
0x50
0x45
0x3C
0x1E
0x3C
0x2D
0x02
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