SEG04G72B1BC2MT-30R Datasheet, PDF (2/16 Pages) List of Unclassifed Manufacturers – 4GB DDR2 . SDRAM registered SO-RDIMM

preliminary Data Sheet
Rev.0.9 07.01.2013
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Registered Dual-In-line
Memory Module (SO-RDIMM) which is organized as x72 high speed CMOS memory arrays. A Register
component and a PLL chip reduce loading on the clock and command/address bus. The module uses DDR2
SDRAM devices with eight internal banks. The module uses double data rate to achieve high-speed operation.
DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2
SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge
function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The
DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high
effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all
full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR2 SDRAMs used
18 x 256M x 8bit (2048Mbit)
Row
Addr.
15
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k
S0#, S1#
Module Dimensions
in mm
67.6 (long) x 30.0(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SEG04G72B1BC2MT-30R
Module Density Transfer Rate
2 GB
5.3 GB/s
Clock Cycle/Data bit
rate
3.0ns / 667MT/s
Latency
5-5-5
Pin Name
A0 - A14
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0-DM8
RAS#
CAS#
WE#
CKE0 / CKE1
CK0
CK0#
DQS0 - DQS8
DQS0# - DQS8#
S0# / S1#
Reset#
VDD
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Supply Voltage (1.8V± 0.1V)
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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