SEG04G72B1BC2MT-30R Datasheet, PDF (11/16 Pages) List of Unclassifed Manufacturers – 4GB DDR2 . SDRAM registered SO-RDIMM

preliminary Data Sheet
Rev.0.9 07.01.2013
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
ODT power-down exit latency
ODT enable from MRS
command
Exit active power-down to READ
command, MR [bit 12 = 0]
Exit active power-down to READ
command, MR [bit 12 = 1]
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
SYMBOL
t_AXPD
T_MOD
t_XARD
t_XARDS
t_XP
t_CKE
5300-555
MIN
MAX
8
12
2
7 – AL
2
3
Unit
tCK
ns
tCK
tCK
tCK
tCK
Register Specifications
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Symbol
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
VOH
VOL
II
IDD
Pins
Address,
control,
command
Address,
control,
command
Address,
control,
command
Address,
control,
command
Parity
output
Parity
output
All pins
All pins
IDD
All pins
IDDD
n/a
IDDD
n/a
CI
Data
CI
RESET#
Conditions
SSTL_18
Min
VREF(DC) +
125
SSTL_18
0
SSTL_18
VREF(DC) +
250
SSTL_18
0
LVCMOS
1.2
LVCMOS
-
VI = VDDQ or VSSQ
-5
RESET# = VSSQ (IO = 0)
-
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
-
IO = 0
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
-
switching 50% duty cycle
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle;
-
One data input switching at
tCK/2, 50% duty cycle
VI = VREF ±250mV;
VDDQ = 1.8V
2.5
VI = VDDQ or VSSQ
-
Max
Units
VDDQ + 250 mV
VREF(DC) - 125 mV
VDD
mV
VREF(DC) - 250 mV
-
V
0.5
V
+5
µA
100
µA
40
mA
Varies by
manufacturer
µA
Varies by
manufacturer
µA
3.5
pF
Varies by
manufacturer
pF
Notes: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2
SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the
module. Detailed information for this register is available in JEDEC standard JESD82.
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Fon: [phone]
Fax: [phone]
www.swissbit.com
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