EMP202 Datasheet, PDF (8/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1. Mixer Registers
Bit
15
14:10
9
8
7
6
5
4
3
2
1
0
5.1.1.MX00 Reset
Default: 6A90H
Writing any value to this register will start a register reset, and causes all of the registers to revert to
their default values. The written data is ignored. Reading this register returns the ID code of the
specific part.
Type
-
R
R
R
R
R
R
R
R
R
R
R
Function
Reserved
3D Code
Read as 1 (Support 20-bit ADC)
Read as 0
Read as 1 (Support 20-bit DAC)
Read as 0 (Support 18-bit DAC)
Read as 0 (No Loudness support)
Read as 1 (Support Headphone output)
Read as 0 (No simulated stereo, for analog 3D block use)
Read as 0 (No Bass & Treble Control)
Read as 0 (No Modem Line support)
Read as 0 (No Dedicated Mic PCM input channel)
5.1.2.MX02 Master Volume
Default: 8000H
These registers control the overall volume level of the output functions. Each step on the left and right
channels corresponds to 1.5dB in increase/decrease in volume.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
14:13
-
Reserved
12:8
R/W
Master Left Volume: (ML[4:0]) in 1.5 dB steps
7:5
-
Reserved
4:0
R/W
Master Right Volume: (MR[4:0]) in 1.5 dB steps
1) For MR/ML: 00h 0 dB attenuation
1Fh 46.5 dB attenuation
2) MR/ML are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when the 6th bit is
written with a 1, it is the equivalent to writing the low 5-bits with 1. For example, writing 1xxxxx will read back
01111.
7/15/2002
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