EMP202 Datasheet, PDF (24/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
6.2.6.AC-Link Low Power Mode Timing
SYNC
BIT_CLK
Slot 1
Slot 2
SDATA_OUT
SDATA_IN
Write to
0x20
Data PR4
Don't care
Ts2_pdown
Note: BIT_CLK not to scale
AC-Link low power mode timing diagram
Parameter
End of slot 2 to BIT_CLK, SDATA_IN low
6.2.7.ATE Test Mode
Symbol
Min
Typical
Ts2_pdown
-
-
Max
1.0
Units
us
RESET#
SDATA_OUT
SDATA_IN, BIT_CLK
Toff
Tsetup2rst
Hi-Z
ATE test mode timing diagram
To meet AC’97 rev2.2 requirements, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in
test mode.
Parameter
Setup to trailing edge of RESET# (also applies to
SYNC)
Rising edge of RESET# to Hi-Z delay
Symbol
Min Typical Max
Tsetup2rst 15.0
-
-
Toff
-
-
25.0
Units
ns
ns
6.2.8.AC-Link IO Pin Capacitance and Loading
Output Pin
BIT_CLK (must support ≥ 2 CODECs)
SDATA_IN
1 CODEC
47.5pF
47.5pF
2 CODEC
62.5pF
55pF
3 CODEC
75pF
60pF
4 CODEC
85pF
62.5pF
6.2.9.BIT-CLK and SDATA-IN State
When RESET# is active, BIT-CLK and SDATA-IN must be floating by internal pull low 100K resistors.
The ac-link signals are driven by another AC’97 on CNR board. This requirement is not mentioned in
AC’97 specifications Rev 2.1. Please refer to CNR (Communication Network Riser) specifications
Rev. 1.0 pages 23~25 or AC’97 Rev. 2.2 for detailed information.
7/15/2002
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