EMP202 Datasheet, PDF (22/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
6.2.2.Warm Reset
SYNC
BIT_CLK
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK Startup
delay
Tsync_high
Tsync_2clk
Warm reset timing diagram
Symbol
Tsync_high
Tsync2clk
Min
1.0
162.8
Typical
1.3
-
6.2.3.AC-Link Clocks
SYNC
Tsync_high
Tsync_2clk
BIT_CLK
BIT_CLK and SYNC timing diagram
Parameter
Symbol
Min
BIT_CLK frequency
-
BIT_CLK period
Tclk_period
-
BIT_CLK output jitter
-
BIT_CLK high pulse width (note 1)
Tclk_high
36
BIT_CLK low pulse width (note 1)
Tclk_low
36
SYNC frequency
-
SYNC period
Tsync_period
-
SYNC high pulse width
Tsync_high
-
SYNC low pulse width
Tsync_low
-
Note 1: Worse case duty cycle restricted to 45/55.
Typical
12.288
81.4
750
40.7
40.7
48.0
20.8
1.3
19.5
EMPIA Technology
Max
Units
-
us
-
ns
Max
Units
-
MHz
-
ns
750
ps
45
ns
45
ns
-
KHz
-
us
-
us
-
us
7/15/2002
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