EMP202 Datasheet, PDF (23/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
6.2.4.Data Output and Input Times
tco
T _setup
BIT_CLK
V _ih
SDATA_OUT
SDATA_IN
SYNC
V _il
V_oh
V_ol
T _hold
Data Output and Input timing diagram
Parameter
Symbol
Min
Typical Max Units
Output Valid Delay from rising edge of BIT_CLK
tco
-
-
15
ns
Input Setup to falling edge of BIT_CLK
tsetup
10
-
-
ns
Input Hold from falling edge of BIT_CLK
thold
10
-
-
ns
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the Device driving the output.
Note 2: 50pF external load
Note 3: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
6.2.5. Signal Rise and Fall Times
BIT_CLK
Triseclk
Tfallclk
SDATA_IN
Trisedin
Tfalldin
Signal Rise and Fall timing diagram
Parameter
Symbol
Min
BIT_CLK rise time
Triseclk
-
BIT_CLK fall time
Tfallclk
-
SYNC rise time
Trisesync
-
SYNC fall time
Tfallsync
-
SDATA_IN rise time
Trisedin
-
SDATA_IN fall time
Tfalldin
-
SDATA_OUT rise time
Trisedout
-
SDATA_OUT fall time
Tfalldout
-
Note 1: 75pF external load
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
Typical
-
-
-
-
-
-
-
-
Max Units
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
7/15/2002
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