EMP202 Datasheet, PDF (26/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
8. Design Suggestions
8.1. Clocking
The clock source for different configurations is listed below.
CODEC ID[1:0]
00
01,10,11
BIT-CLK
Output
BIT CLK
Clock source
Crystal or external clock (XTAL-IN) BITCLK is output
BIT CLK always an input, XTAL-IN (pin 2) ignored
8.2. AC-Link
When the EMP202 takes serial data from the AC’97 controller, it samples SDATA_OUT on the falling
edge of BIT_CLK. When the EMP202 sends serial data to the AC’97 controller, it starts to drive
SDATA_IN on the rising edge of BIT_CLK.
The EMP202 will return any uninstalled bits or registers with 0 for read operations. The EMP202 also
stuffs the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified.
Please refer to “Audio CODEC ’97 Component Specification Revision 2.2” for details
SYNC
OUTGOING STREAMS
TAG
CMD
ADR
CMD PCM
DATA LEFT
PCM
RT
NA
PCM PCM
PCM
PCM
CTR LSURR RSURR LFE
PCM
LALT
PCM
RALT
RSVD
INCOMING STREAMS
TAG
STATUS STATUS PCM
ADR
DATA LEFT
PCM
RT
NA
NA RSVD RSVD RSVD RSVD RSVD RSVD
TAG PHASE
DATA PHASE
5.1 Channel Slot Arrangement Defined in AC’97 Specification rev2.2
8.3. Reset
There are 3 types of reset operations: Cold, Warm and Register reset, which are listed below:
Reset Type
Trigger condition
CODEC response
Cold
Assert RESET# for a specified period
Reset all hardware logic and all registers to their
default value.
Warm
Driven SYNC high for specified period
Reactivates AC-LINK, no change to register
without BIT_CLK
values.
Register
Write register indexed 00h
Reset all registers to their default value.
The AC’97 controller should drive SYNC and SDATA-OUT low during the period of RESET#
assertion to guarantee that the EMP202 resets successfully.
7/15/2002
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