EMP202 Datasheet, PDF (16/28 Pages) List of Unclassifed Manufacturers – Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems

Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
Bit
15:14
13:12
11:10
9
8:6
5:4
3
2
1
0
5.1.18. MX28 Extended Audio ID
Default: 0607H
Type
R
-
R
R
NA
R/W
-
R
R
R
Function
ID[1:0]: 00=XTAL Out grounded
ID13, ID0#=XTAL OUT crystal or floating
Reserved, read as 0
REV[1:0]=01 to indicates EMP202 is AC’97 rev2.2 compliant.
AMAP: Read as 1 (DAC mapping base on CODEC ID)
Reserved, read as 0
DSA{1:0], DAC Slot Assignment
ID[1:0]=00 – DSA[1:0] reset =00 where left slot 3, right slot 4
ID[1:0]=01 – DSA[1:0] reset =01 where left slot 7, right slot 8
ID[1:0]=10 – DSA[1:0] reset =01 where left slot 6, right slot 9
ID[1:0]=11 – DSA[1:0] reset =10 where left slot 10, right slot 11
Reserved, read as 0
SPDIF: Read as 1 (S/PDIF is supported)
DRA: Read as 1 (Double Rate Audio is supported)
VRA: Read as 1 (Variable Rate Audio is supported)
5.1.19. MX2A Extended Audio Status and Control
Default: 01F0H
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2
are read/write bits which are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5
are read/write bits used to determine the AC-LINK slot assignment of the S/PDIF. Bit 10 is a read only
bit which tells the controller if the S/PDIF configuration is valid.
Bit Type
Function
15:11 NA Reserved
10
R
SPCV: (S/PDIF Configuration Valid).
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid
9:6
NA Reserved
5:4
R/W SPSA[1:0]: (S/PDIF Slot Assignment).
00: S/PDIF source data assigned to AC-LINK slot3/4.
01: S/PDIF source data assigned to AC-LINK slot7/8.
10: S/PDIF source data assigned to AC-LINK slot6/9.
11: S/PDIF source data assigned to AC-LINK slot10/11 (default).
3
-
Reserved
2
R/W SPDIF Enable:
1: Enable
0: Disable (Hi-Z)
1
-
Reserved
0
R/W VRA Enable:
1: Enable
0: Disable
1) If VRA = 0, the EMP202 AD/DA operates at a fixed 48KHz sampling rate. Otherwise, it operates with variable
sampling rates as defined in MX2C and MX32.
2.) If pin 48 is held high at power up, SPDIF is not available and D15:D1 cannot be written and will read back 0.
7/15/2002
16