RFM66W Datasheet, PDF (71/87 Pages) List of Unclassifed Manufacturers – 868 & 915MHz Ultra Low Power High Link Budget Integrated UHF Transceiver

WIRELESS & SENSING
RFM66W
DATASHEET
Name
(Address)
Bits
RegRes17
7-0
to
RegRes19
RegAfcFei
7-5
(0x1a)
4
3
2
1
0
RegAfcMsb
7-0
(0x1b)
RegAfcLsb
7-0
(0x1c)
RegFeiMsb
7-0
(0x1d)
RegFeiLsb
7-0
(0x1e)
RegPreambleDete 7
ct
(0x1f)
6-5
4-0
RegRxTimeout1 7-0
(0x20)
RegRxTimeout2 7-0
(0x21)
RegRxTimeout3 7-0
(0x22)
Variable Name
reserved
unused
AgcStart
reserved
unused
AfcClear
AfcAutoClearOn
AfcValue(15:8)
AfcValue(7:0)
FeiValue(15:8)
FeiValue(7:0)
PreambleDetectorOn
PreambleDetectorSize
PreambleDetectorTol
TimeoutRxRssi
TimeoutRxPreamble
TimeoutSignalSync
Mode
Default
value
Description
rw 0x47 reserved. Keep the Reset values.
0x32
0x3E
r
- unused
wp 0x00 Triggers an AGC sequence when set to 1.
rw 0x00 reserved
-
- unused
wp 0x00 Clear AFC register set in Rx mode. Always reads 0.
rw 0x00 Only valid if AfcAutoOn is set
0 → AFC register is not cleared at the beginning of the
automatic AFC phase
1 → AFC register is cleared at the beginning of the automatic
AFC phase
rwx 0x00 MSB of the AfcValue, 2‟s complement format. Can be used to
overwrite the current AFC value
rwx 0x00 LSB of the AfcValue, 2‟s complement format. Can be used to
overwrite the current AFC value
rwx - MSB of the measured frequency offset, 2‟s complement
rwx - _{LSB of the measured frequency offset, 2‟s complement}
Frequency error = FeiValue x Fstep
rw 0x00 Enables Preamble detector when set to 1. The AGC settings
supersede this bit during the startup / AGC phase.
0 → Turned off
1 → Turned on
rw 0x02 Number of Preamble bytes to detect to trigger an interrupt
00 → 1 byte
10 → 3 bytes
01 → 2 bytes
11 → Reserved
rw 0x00 Number or chip errors tolerated over PreambleDetectorSize.
4 chips per bit.
rw 0x00 Timeout interrupt is generated TimeoutRxRssi*16*T_bit after
switching to Rx mode if Rssi interrupt doesn‟t occur (i.e.
RssiValue > RssiThreshold)
0x00: TimeoutRxRssi is disabled
rw 0x00 Timeout interrupt is generated TimeoutRxPreamble*16*T_bit
after switching to Rx mode if Preamble interrupt doesn‟t occur
0x00: TimeoutRxPreamble is disabled
rw 0x00 Timeout interrupt is generated TimeoutSignalSync*16*T_bit
after the Rx mode is programmed, if SyncAddress doesn‟t
occur
0x00: TimeoutSignalSync is disabled
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