RFM66W Datasheet, PDF (51/87 Pages) List of Unclassifed Manufacturers – 868 & 915MHz Ultra Low Power High Link Budget Integrated UHF Transceiver

WIRELESS & SENSING
RFM66W
DATASHEET
Rx DATA
(NRZ)
Bit N-x =
Sync_value[x]
DCLK
Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
SyncAddressMatch
Figure 27. Sync Word Recognition
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
5.2.3.2. Configuration
 _{Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode}
this ^{field is also used for Sync word generation in Tx mode.}
 Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync
word generation in Tx mode.
Note SyncValue choices containing 0x00 bytes are not allowed
5.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.
5.2.5. Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the RFM66W, and their configuration in Continuous or Packet mode
is controlled through RegDioMapping1 and RegDioMapping2.
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