RFM66W Datasheet, PDF (47/87 Pages) List of Unclassifed Manufacturers – 868 & 915MHz Ultra Low Power High Link Budget Integrated UHF Transceiver

WIRELESS & SENSING
RFM66W
DATASHEET
5. Data Processing
5.1. Overview
5.1.1. Block Diagram
Figure below illustrates the RFM66W data processing circuit. Its role is to interface the data to/from the modulator/
demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
Tx/Rx
CONTROL
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Data
Rx _SYNC
RECOG.
Tx
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Potential datapaths (data operation mode dependant)
Figure 23. RFM66W Data Processing Conceptual View
The RFM66W implements several data operation modes, each with their own data path through the data processing
section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.
5.1.2. Data Operation Modes
The RFM66W has two different data operation modes selectable by the user:
 Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be
used if adequate external signal processing is available.
 Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically
built with preamble, Sync word, and optional CRC and DC-free encoding schemes The reverse operation is performed
in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on
the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited.
Each of these data operation modes is fully described in the following sections.
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