RF65 Datasheet, PDF (61/72 Pages) List of Unclassifed Manufacturers – Low Power Integrated UHF Receiver With -120dBm High Sensitivity

ADVANCED COMMUNICATIONS & SENSING
RF65
DATASHEET
RegIrqFlags2
(0x28)
7 FifoFull
6 FifoNotEmpty
5 FifoLevel
4 FifoOverrun
3-
2 PayloadReady
1 CrcOk
0 LowBat
RegRssiThresh
(0x29)
RegRxTimeout1
(0x2A)
7-0 RssiThreshold
7-0 TimeoutRxStart
RegRxTimeout2
(0x2B)
7-0 TimeoutRssiThresh
r
0 Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
r
0 Set when FIFO contains at least one byte, else cleared
r
0 Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
rwc
0 Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
reception.
r
0 unused
r
0 Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared, is Ok). Cleared when FIFO is empty.
r
0 Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
rwc
- Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set by the user.
rw 0xE4 RSSI trigger level for Rssi interrupt :
* - RssiThreshold / 2 [dBm]
rw
0x00 Timeout interrupt is generated TimeoutRxStart*16*T_bit
after switching to Rx mode if Rssi interrupt doesn‟t occur
(i.e. RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
rw
0x00 Timeout interrupt is generated TimeoutRssiThresh*16*T_bit
after Rssi interrupt if PayloadReady interrupt doesn‟t
occur.
0x00: TimeoutRssiThresh is disabled
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